This work simulates the performance of 4H-SiC MESFETs and establishes the optimum device structure for dc and rf applications that operate at high voltages.Devices with various channel doping,buffer layer doping,recess thickness,gate-to-drain spacing and temperatures of operation are considered.The simulation results reveal that a p-type buffer layer of 5×10^(15) cm^(−3) and a channel layer of 1×10^(17) cm^(−3 )yield favorable results.The cut-off frequency is 22.53 GHz,the maximum transconductance is 50.55 mS/mm,the drain saturation current is 239.76 mA/mm and the breakdown voltage is 70.40 V.The breakdown voltages increase to 90.2 V as the gate-to-drain spacing increases to 1µm.Based on these simulation results,new 4H-SiC MESFET designs can be calibrated.
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机译：Anomalously anisotropic channel mobility on trench sidewalls in 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors fabricated on 8 degrees off substrates
机译：Anomalously anisotropic channel mobility on trench sidewalls in 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors fabricated on 8 deg off substrates
机译：Anomalously anisotropic channel mobility on trench sidewalls in 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors fabricated on 8° off substrates
